Sankar Basu
$500,000
Arizona State University
Arizona
Computer and Information Science and Engineering (CISE)
This award is funded in whole or in part under the American Rescue Plan Act of 2021 (Public Law 117-2).<br/><br/>Over past decades, there have existed grand challenges in developing high performance and energy-efficient computing solutions for big-data processing. Meanwhile, owing to the boom in artificial intelligence (AI), especially Deep Neural Networks (DNNs), such big-data processing requires efficient, intelligent, fast, dynamic, robust, and on-device adaptive cognitive computing. However, those requirements are not sufficiently satisfied by existing computing solutions due to the well-known power wall in silicon-based semiconductor devices, the memory wall in traditional Von-Neuman computing architectures, and computation-/memory-intensive DNN computing algorithms. This project aims to foster a systematic breakthrough in developing AI-in-Memory computing systems, through collaboratively developing ahybrid in-memory computing (IMC) hardware platform integrating the benefits of emerging non-volatile resistive memory (RRAM) and Static Random Access Memory (SRAM) technologies, as well as incorporating IMC-aware deep-learning algorithm innovations. The overarching goal of this project is to design, implement, and experimentally validate a new hybrid in-memory computing system that is collaboratively optimized for energy efficiency, inference accuracy, spatiotemporal dynamics, robustness, and on-device learning, which will greatly advance AI-based big-data processing fields such as computer vision, autonomous driving, robotics, etc. The research will also be extended into an educational platform, providing a user-friendly learning framework, and will serve the educational objectives for K-12 students, undergraduate, graduate, and under-represented students.<br/><br/>This project will advance knowledge and produce scientific principles and tools for a new paradigm of AI-in-Memory computing featuring significant improvements in energy efficiency, speed, dynamics, robustness, and on-device learning capability. This cross-layer project spans from device, circuit, and architecture to DNN algorithm exploration. First, a hybrid RRAM-SRAM based in-memory computing chip will be designed, optimized, and fabricated. Second, based on this new computing platform, the on-device spatiotemporal dynamic neural network structure will be developed to provide an enhanced run-time computing profile (latency, resource allocation, working load, power budget, etc.), as well as improve the robustness of the system against hardware intrinsic and adversarial noise injection. Then, efficient on-device learning methodologies with the developed computing platform will be investigated. In the last thrust, an end-to-end DNN training, optimization, mapping, and evaluation CAD tool will be developed that integrates the developed hardware platform and algorithm innovations, for optimizing the software and hardware co-designs to achieve the user-defined multi-objectives in latency, energy efficiency, dynamics, accuracy, robustness, on-device adaption, etc.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.