Xiaogang (Cliff) Wang
$173,000
California State University-Long Beach Foundation
California
Computer and Information Science and Engineering (CISE)
The enormous consequences of hardware vulnerabilities, including the costly prospect of fixing them, have been the subject of dozens of national reports. This project aims to address these growing issues. Particularly, the project’s novelty is conceptualizing hardware security and reliability based on the notion of reconfigurability under realistic attack models and a unified definition of different hardware security requirements. The project's broader significance and importance include helping the national electronics industry safeguard the underlying hardware for a trustworthy information age and increasing the number of minorities seeking undergraduate and graduate degrees in science and engineering, with a focus on cybersecurity.<br/><br/>In a fabless paradigm, integrated circuit design houses must envision not only traditional fault-tolerance techniques to reduce the cost of replacing defective components, but also procedures to avoid piracy and overproduction of their designs as well as mitigate potentially inserted hardware Trojans by untrusted foundries. In this project, the investigator and his team focus on a comprehensive hardware security and reliability framework in two phases. First, the research team investigates secure embedded Field-Programmable Gate Array (eFPGA) redaction solutions. The structure of eFPGAs can provide opportunities to make the integrated circuits secure not just against logic locking attacks but also to mitigate hardware Trojans and tolerate faults at run-time. Second, the research team propose dynamic key schemes with multi-level activation and functional stages to offer a high degree of logic locking security, hardware Trojan mitigation, and fault tolerance without significantly imposing area and power overheads. The outcomes of this project will be disseminated to well-respected design automation venues, and an open-source computer program will be released that receives an efficient digital circuit and outputs a low-overhead and provably secure netlist considering different hardware security requirements. This will help the national high-tech industry thrive and contribute to economic prosperity, innovation, and security.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.